This invention relates generally to wireless communication devices. More particularly, this invention relates to a reconfigurable digital wireless communication device.
Existing communication devices are xe2x80x9cstaticxe2x80x9d devices. That is, they are designed to support a specific wireless communication standard and/or to support a specific application (e.g., voice, data transmission) at a specific data rate. Typically, different wireless communication standards are used in different wireless networks, both within a geographic locality and worldwide. Thus, an individual traveling between different regions is required to use a separate wireless communication device in each region.
In addition, the advent of new and evolving user applications and services may necessitate redesign of static wireless communication infrastructure and terminals. Thus, an individual or service provider who wants to utilize or enable such services is required to replace or upgrade equipment.
FIG. 1 illustrates a digital communication modem 20 that may be implemented in accordance with prior art approaches to multi-standard communication devices. A transmitter 22 transmits a signal to a channel 24, which may be a wireless or physical channel. The transmitted signal is received at the modem 20, where it is initially processed by a Radio Frequency (RF) subsystem 26. The RF subsystem 26 performs analog mixing, analog filtering, and analog gain control functions. The analog signal from the RF subsystem 26 is then converted to an equivalent digital signal by an analog-to-digital converter 28.
The digital signal is then processed by a digital front-end processing circuit 30, which performs standard-specific, channel-specific, and modulation-specific bandwidth selection, filtering, sampling-rate control and other signal processing. The signal from the digital front-end processing circuit 30 is then passed to a detector/demodulator circuit 32, which performs signal detection and demodulation operations. The detection and demodulation circuit 32 also interacts with a parameter estimation circuit 34. The output from the detection and demodulation circuit 32 is subsequently processed by a channel decoder 36 and then a source decoder 38.
FIG. 2A shows a prior art architecture for implementing the structure of FIG. 1. An RF subsystem 26 is again used to provide one or more bandpass signals (intermediate frequency signals), which are then digitized by the analog-to-digital converter 28, which is typically implemented as a free-running analog-to-digital converter. The output from the analog-to-digital converter 28 is placed on a bus 52. Signals from the bus 52 are routed to hardware processors 60 and software programmable processors 70. The hardware processors include programmable logic device 62 and fixed-function logic 64. The software programmable processors include digital signal processor 72 and microprocessor 74.
The digital components (30, 32, 34, 36, and 38) of the device 20 are typically implemented on software-programmable processors 70, or as a fully hardwired, non-programmable application-specific integrated circuit 64. The hardwired circuit may be augmented by a programmable logic device 62, which provides limited fine-granularity programmability. The device 50 of FIG. 2A facilitates the management of functions executing on the programmable logic device 62 via controlling the download of functionality into the programmable logic device 62 and control of the dataflow into and out of the programmable logic device 62. The software-programmable processors 70 typically comprises a digital signal processor 72 and a control microprocessor 74. For lower bandwidth applications (tens of kbps), software-programmable digital signal processors 72 are typically used to perform requisite signal processing functions. For high bandwidth applications (tens of Mbps), a fully hardwired approach is typically employed. The general purpose microprocessor 74 typically performs control and other functions. Accordingly, the signal processing device 50 can be highly optimized only for a particular communication standard, service and application. Prior art approaches to accommodating multiple standards, services and applications have essentially consisted of combining the disparate hardware and software resources separately optimized for each service of interest. This results in poor efficiency in terms of size, weight and power consumption.
FIG. 2B illustrates the control architecture 80 for a prior art multi-standard communication apparatus. The architecture 80 includes executive code 88, which is effectively an operating system running on microprocessor 74 or digital signal processor 72. One of a suite of applications 84 is selected to run under the operating system. Each application 84 executes a set of software/hardware functions 82A-C. Each application 84 requires computation resources, which are available according to FIG. 2A, either via a microprocessor, a digital signal processor, a fixed-function logic engine, or a programmable logic engine. Thus, each of the applications requires some combination of these resources; the actual partitioning among their use is determined by the product/application requirements. For example, operation on a portable device favors much of the functionality being implemented on dedicated, fixed-function hardwired logic devices. On the other hand, product flexibility and upgrade-ability requires use of completely programmable components in the platform, such as microprocessors, digital signal processors, and programmable logic. The approach of FIG. 2B is also inefficient, as it essentially relies upon sequentially selecting one of the sets of disparate and redundant hardware and software resources discussed in connection with FIG. 2A.
The poor efficiency of the prior art approaches discussed is evident from FIG. 3, which depicts energy efficiency vs. flexibility for the various architectural elements of device 50. The highly efficient fixed-hardware resources are highly inflexible, so that considerable replication (and therefore redundancy) is incurred. At the opposite extreme, the highly flexible programmable logic devices, embedded processors and software-programmable digital signal processors (DSPs) that may be employed are inefficient with respect to power and size. These design tradeoffs result in the Energy-Efficiency Gap 92 shown in FIG. 3.
In view of the foregoing, it would be highly desirable to provide a single wireless communication device that can efficiently and cost-effectively support multiple wireless communication standards and applications.
A digital wireless communication device comprises a software-programmable processor, a heterogeneous reconfigurable multiprocessing logic circuit, and a bus connecting the software-programmable processor and the heterogeneous reconfigurable multiprocessing logic circuit. The software-programmable processor is selected from the group comprising: a digital signal processor and a central processing unit. The heterogeneous reconfigurable multiprocessor comprises a set of heterogeneous signal processing kernels and a reconfigurable data router interconnecting the heterogeneous signal processing kernels. The signal processing kernels and data router are controlled by the software-programmable processor via control busses. The design of the heterogeneous reconfigurable multiprocessor is aided by an analysis method referred to as profiling.
The invention establishes a new architecture for multiple-service, multiple-standard digital communication devices. The platform enables the same hardware resources to be reconfigured in order to provide more flexible delivery of arithmetic and control operations via techniques of heterogeneous reconfigurable multiprocessing. The architecture is reprogrammable through the control of software resident on or downloaded into memory, which may be used by the microprocessor, digital signal processor, or heterogeneous reconfigurable multiprocessing logic. The architecture facilitates new, broadband services over a wireless or wired communication network on a single hardware platform at the base station (infrastructure end) or the user terminal (consumer terminal end).
The invention provides a communication apparatus that can operate over a plurality of telecommunication physical layer standards, radio frequency bands, data-rates, and user-programmed or network-programmed services. The functionality of a device constructed in accordance with the invention is defined as a set of software modules, each including a combination of xe2x80x9cpersonalitiesxe2x80x9d for the hardware devices of the apparatus. The software modules comprise object code that executes on a microprocessor, a digital signal processor, or on a heterogeneous reconfigurable multiprocessing logic module. The invention enables the use of a single hardware platform to operate over a variety of bands, standards, and data rates, while delivering a variety of user-programmed or network-programmed services. Furthermore, the invention can be reconfigured in the factory or field through various means including but not limited to factory/point-of-sale programming, remote control, and over-the-air or over-the-network download.
Thus, the invention significantly reduces the number of product platforms required to span a large product offering space for the wired or wireless communication market.